A memristive Hopfield network for associative memory

doi:10.1038/protex.2015.070

Method Article

A memristive Hopfield network for associative memory

https://doi.org/10.1038/protex.2015.070

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This protocol presents an approach to realize associative memory in a memristive Hopfield network (MHN). In the MHN, neurons and synapse are constructed with operational amplifiers and memristors, respectively; and control signals are provided by field programming gate array (FPGA). Different patterns can be stored into the MHN by appropriately setting the synaptic weight matrix and threshold matrix. In the process to recall the pre-stored pattern, the states of the neurons in the MHN are asynchronously updated in sequence under the control of FPGA.

Materials science

Mathematics and computing

Neuroscience

Associative memory

Hopfield network

memristor

An artificial neural network (ANN) is a bio-inspired information processing paradigm, which has been proved useful in many applications, such as pattern recognition, speech production, real time control, and etc.¹ The Hopfield neural network is one of the most studied ANN^2-5, and its structure can be implemented by an electronic circuit⁶. Although many attempts have been made to simulate or construct ANNs with the ultimate goal to emulate the human brain⁷, there are still many challenges. In biological systems, learning involves adjustments of the synaptic weights (connections) between two adjacent neurons, and the ANNs process information in a similar way. An ideal synapse in the ANN should be reconfigurable, nonvolatile, scalable and low-power. Some types of devices (such as resistor, capacitor and current source⁸) proposed in the early stage cannot completely satisfy the rigorous requirements of synapses. Recently, memristor⁹, which takes advantages of reconfigurability, high-scalability, and low-power consumption⁹, has been demonstrated to be an promising candidate for constructing synapses^10-14. However, constructing ANN with memristors is still of great challenge^15-20.

In this protocol, we present an approach to demonstrate associative memory in a memristive Hopfield network (MHN). Through an appropriate design of synaptic weight matrix and threshold matrix, pattern(s) can be stored into the MHN, and the pre-stored pattern(s) can be successfully retrieved.

In the experiment of the Hopfield MHN, the following equipment and components are used: Keithley-4200 semiconductor characterization system, transmission-gate chips (Texas Instruments CD4066), operational amplifiers (Texas Instruments LM324N), comparator chip (Texas Instruments LM339), field programming gate array (FPGA, model no. ALTERA EP2C8Q208C8), RIGOL oscilloscope (model no. DS4024), memristors in standard 28-pin dual in-line package (DIP), capacitors, resistors, ribbon wires, and printed circuit board (PCB). In the design and simulation of a more complicated MHN consisting of 6561 synapses, IC design software and database (Cadence 5141 and standard 0.18 μm CMOS process library) are used.

Fabrication of the MHN

The MHN was fabricated on a printed circuit board (PCB). The synapse consists of a memristor, a resistor, an inverter and a transmission gate. Positive or negative synaptic weight can be obtained by electronic switches. In the 3-bit MHN, a neuron consists of three synapses. A neuron was constructed with an operational amplifier to obtain the sum of the three inputs. The state of the neuron was stored on a capacitor. The fabrication procedure of the MHN is as follows: design of the schematic circuit of the MHN; design of the PCB layout of the MHN (see "Figure 1":http://www.nature.com/protocolexchange/system/uploads/3655/original/Figure_1.jpg?1432391113 ); assembly of the commercial chips, resistors and capacitors, onto the PCB; wire connection of the memristors with the PCB; and programming of the FPGA to control the MHN.

TIP: There are two possible circuit configurations for the synaptic connection, as shown in "Figure 2":http://www.nature.com/protocolexchange/system/uploads/3657/original/Figure_2.jpg?1432391117. In the first configuration (Figure 2(a)), the synaptic weight of the synapse corresponding to input N_i (i=1, 2, 3) is w_i=± R /(M_i + R), where M_i is the resistance of the corresponding memristor. In this design, R should be of a high resistance at the level of 10⁶ ohms in order to limit the current and avoid wrongly-switching of the memristor during circuit operation. M_i can only be adjusted in the range from several tens of ohms to several hundreds of kΩ due to the memristor inherent property. As R is much larger than M_i, w_i would be insensitive to M_i and may always stay at ±1. Thus the variable range of the synaptic weight is very small. It is difficult for the MHN to detect such a small change in w_i. In contrast, in the second configuration (Figure 2(b)), w_i=± M_i/(M_i + R), thus the synaptic weight w_i is much more sensitive to the change of M_i and can be varied in a larger range. Therefore, the circuit configuration shown in Figure 2(b) is used to implement the synapses.

Implementation of associative memory in the MHN

With a given pattern, the synaptic weight matrix elements in equation (1) (all equations in this protocol are placed in the "Supplementary document 1":http://www.nature.com/protocolexchange/system/uploads/3659/original/Supplementary_equation_file.pdf?1432386669) are set to w₁₁= w₂₂= w₃₃=0, w₁₂= w₂₁, w₁₃= w₃₁, and w₂₃= w₃₂. The threshold vector T=(θ₁ θ₂ θ₃) is set as θ₁= θ₂= θ₃= θ. Here, w_ij (i, j=1, 2, 3) is in the form of equation (2). During the recalling process, the MHN is updated according to equation (3). In equation (3), t denotes the number of updating cycles; t=0 denotes no updating taking place and the corresponding state vector is the initial vector X(0); and the sign function is defined in equation (4). In one updating cycle, new states of the neurons are asynchronously updated from x₁, x₂ to x₃ in three stages, which are defined as stages a, b and c, respectively.

Single associative memory

It is required that if the input is the target pattern itself, the final output must also stabilize at the target pattern. Thus, when “110” is stored into the MHN, according to equation (3) and Hopfield network rule for updating, equation (5) should be satisfied. With w₁₁= w₂₂= w₃₃=0, w₁₂= w₂₁, w₁₃= w₃₁, and w₂₃= w₃₂ and θ₁= θ₂= θ₃= θ, equation (5) is simplified as shown in equation (6). Equation (6) can be satisfied with the following setting: θ=-2/60, w₁₂=4/60, w₁₃=1/60, and w₂₃=-4/60. Thus the synaptic weight matrix is given by equation (7), and the threshold vector is given by equation (8). The following initial states X(0) along with equations (7) and (8) are put into equation (3) to verify the convergence: “000”, “001”, “010”, “011”, “100”, “101”, “110”, and “111”. It is found that the MHN can eventually converge to the final state “110” from the above initial states.

Here, X(0)= (x(0)₁ x(0)₂ x(0)₃)=(0 0 0) is taken as an example to demonstrate the recalling process. In stage a of the first updating cycle, we obtain equation (9) according to equation (3). And only x₁ is updated in stage a of the first updating cycle, and thus we eventually obtain equation (10) in this stage; In stage b of the first updating cycle, equation (11) can be obtained according to equation (3). And only x₂ is updated in stage b, so we eventually obtain equation (12) in this stage; In stage c of the first updating cycle, equation (13) can be obtained according to equation (3). And only x₃ is updated in stage c, and thus we eventually obtain equation (14). From equations (9)-(14), we can see that “000” eventually converges to “110”. In a similar way, the MHN converges to “110” from any other initial states.

With the synaptic weight matrix shown in equation (7), the resistance matrix of the memristors determined from equation (2) can be set to the form of equation (15). Note that it is not necessary to adjust the resistances of the memristors exactly to the above values because the MHN has a tolerance to the resistance variation. An offline training scheme for setting the resistance of the memristors to a pre-determined value is implemented with a C Language program embedded in the Keithley 4200 semiconductor characterization system. With the actual resistance matrix M in equation (16), the actual synaptic weight matrix W was set to equation (17). With the above synaptic weight matrixe W and the threshold vector in equation (8), “110” can be correctly retrieved using the MHN fabricated on the PCB.

Multi-associative memory

Similar to the requirement for single associative memory, when the two patterns “000” and “101”, are stored in the MHN, equations (18) and (19) should be satisfied. With w₁₁= w₂₂= w₃₃= 0, w₁₂= w₂₁, w₁₃= w₃₁, and w₂₃= w₃₂ and θ₁= θ₂= θ₃= θ, equations (18) and (19) are respectively simplified as equations (20) and (21). Equations (20) and (21) can be satisfied with the following setting: θ=6/60, w₁₂=1/60, w₁₃=8/60, and w₂₃=4/60. Thus the synaptic weight matrix is given by equation (22), and the threshold vector is given by equation (23). Putting equations (22) and (23) and X(0) (X(0) can be varied from “000” to “111”) into equation (3), “000” and “101” can be stored into and retrieved from the MHN theoretically. For the synaptic weight matrix given in equation (22), the resistance matrix obtained from equation (2) can be set to the form of equation (24). The actual resistance matrix and the actual synaptic weight matrix of the fabricated MHN are given by equations (25) and (26), respectively:

The time cost to retrieve the pre-stored pattern in the 3-bit MHN depends on the initial state and the operational frequency. At 5 kHz operating frequency, the time required to retrieve the pre-stored pattern ranges from 33.3 μs to 300 μs depending on the initial states.

Failure to set the resistance matrix to the pre-determined one with appropriate precision may lead to the failure of associative memory. In this work, we set the memristors to a low resistance state first with a compliance current (e.g., 0.1 mA, 1 mA, etc.), and then the memristors are programmed with an offline training scheme which is implemented with a C Language program embedded in the Keithley 4200 semiconductor characterization system. In this way, the resistance matrix with appropriate precision can be obtained.

In the associated article, we demonstrated single associative memory and multi-associative memories in a 3-bit MHN. In the 3-bit MHN, the pre-stored pattern(s) can be successfully retrieved at an operating frequency of 5 kHz. On the other hand, the simulation for a more complicated MHN consisting of 6561 synapses shows that more complicated patterns can be stored and retrieved but convergence errors may occur, as described in the associated article.

Ahmad, Z., Mat Noor, R. A. & Zhang, J. Multiple neural networks modeling techniques in process control: a review. Asia-Pac. J. Chem. Eng. 4, 403-419 (2009).
Hopfield, J. J. Neural networks and physical systems with emergent collective computational abilities. Proceedings of the National Academy of Sciences 79, 2554-2558 (1982).
Hopfield, J. J. Neurons with graded response have collective computational properties like those of two-state neurons. Proceedings of the National Academy of Sciences 81, 3088-3092 (1984).
Hopfield, J. J. & Tank, D. W. “Neural” computation of decisions in optimization problems. Biol. Cybern. 52, 141-152 (1985).
Hopfield, J. J. & Tank, D. W. Computing with neural circuits- a model. Science 233, 625-633 (1986).
Wen, U.-P., Lan, K.-M. & Shih, H.-S. A review of Hopfield neural networks for solving mathematical programming problems. European Journal of Operational Research 198, 675-687 (2009).
Cattell, R. & Parker, A. Challenges for Brain Emulation: Why is Building a Brain so Difficult? Natural intelligence 1, 1-28 (2012).
Verleysen, M., Martin, D. & Jespers, P. in 1989 European Conference on Circuit Theory and Design 73-77 (IET, Brighton, 1989).
Hu, S. G. et al. Review of nanostructured resistive switching memristor and its applications. Nanoscience and Nanotechnology Letters 6, 729-757 (2014).
Jo, S. H. et al. Nanoscale memristor device as synapse in neuromorphic systems. Nano Lett. 10, 1297-1301 (2010).
Li, Y. et al. Ultrafast synaptic events in a chalcogenide memristor. Scientific Reports 3, 1619 (2013).
Yu, S., Wu, Y., Jeyasingh, R., Kuzum, D. & Wong, H. S. P. An Electronic Synapse Device Based on Metal Oxide Resistive Switching Memory for Neuromorphic Computation. IEEE Trans. Electron Devices 58, 2729-2737 (2011).
Wang, Z. Q. et al. Synaptic learning and memory functions achieved using oxygen ion migration/diffusion in an amorphous ingazno memristor. Adv. Funct. Mater. 22, 2759-2765 (2012).
Hu, S. G. et al. Synaptic long-term potentiation realized in Pavlov's dog model based on a NiOx-based memristor. J. Appl. Phys. 116, 214502 (2014).
Ziegler, M. et al. An electronic version of Pavlov's dog. Adv. Funct. Mater. 22, 2744-2749 (2012).
Hu, S. G. et al. Design of an electronic synapse with spike time dependent plasticity based on resistive memory device. J. Appl. Phys. 113, 114502-114504 (2013).
Pershin, Y. V. & Di Ventra, M. Experimental demonstration of associative memory with memristive neural networks. Neural Networks 23, 881-886 (2010).
Burr, G. et al. in 2014 IEEE International Electron Devices Meeting (IEDM). 29.25. 21-29.25. 24 (IEEE).
Park, S. et al. in 2013 IEEE International Electron Devices Meeting (IEDM). 25.26.21-25.26.24 (IEEE).
Eryilmaz, S. B. et al. Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array. Frontiers in Neuroscience 8, 205 (2014).

This work was supported by NSFC under project No. 61274086 and the Young Scholar Fund of Sichuan under project No. 2011JQ0002, MOE Tier 1 Grant (Grant No. RG 43/12) and NTU-A*STAR Silicon Technologies Centre of Excellence (Grant No.M4070176.040).

The authors declare no competing financial interests.

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