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Y. Liu

T. P.  Chen

S. G. Hu

Z. Liu

J. J. Wang

Q. Yu

L. J.  Deng

Y. Yin

Sumio Hosaka

Figure 1

Figure 2

A memristive Hopfield network for associative memory

An artificial neural network \(ANN) is a bio-inspired information processing paradigm, which has been proved useful in many applications, such as pattern recognition, speech production, real time control, and etc.1 The Hopfield neural network is one of the most studied ANN2-5, and its structure can be implemented by an electronic circuit6. Although many attempts have been made to simulate or construct ANNs with the ultimate goal to emulate the human brain7, there are still many challenges. In biological systems, learning involves adjustments of the synaptic weights \(connections) between two adjacent neurons, and the ANNs process information in a similar way. An ideal synapse in the ANN should be reconfigurable, nonvolatile, scalable and low-power. Some types of devices \(such as resistor, capacitor and current source8) proposed in the early stage cannot completely satisfy the rigorous requirements of synapses. Recently, memristor9, which takes advantages of reconfigurability, high-scalability, and low-power consumption9, has been demonstrated to be an promising candidate for constructing synapses10-14. However, constructing ANN with memristors is still of great challenge15-20.





In this protocol, we present an approach to demonstrate associative memory in a memristive Hopfield network \(MHN). Through an appropriate design of synaptic weight matrix and threshold matrix, pattern\(s) can be stored into the MHN, and the pre-stored pattern\(s) can be successfully retrieved.

In the experiment of the Hopfield MHN, the following equipment and components are used: Keithley-4200 semiconductor characterization system, transmission-gate chips \(Texas Instruments CD4066), operational amplifiers \(Texas Instruments LM324N), comparator chip \(Texas Instruments LM339), field programming gate array \(FPGA, model no. ALTERA EP2C8Q208C8), RIGOL oscilloscope \(model no. DS4024), memristors in standard 28-pin dual in-line package \(DIP), capacitors, resistors, ribbon wires, and printed circuit board \(PCB). In the design and simulation of a more complicated MHN consisting of 6561 synapses, IC design software and database \(Cadence 5141 and standard 0.18 μm CMOS process library) are used.

**Fabrication of the MHN**


The MHN was fabricated on a printed circuit board \(PCB). The synapse consists of a memristor, a resistor, an inverter and a transmission gate. Positive or negative synaptic weight can be obtained by electronic switches. In the 3-bit MHN, a neuron consists of three synapses. A neuron was constructed with an operational amplifier to obtain the sum of the three inputs. The state of the neuron was stored on a capacitor. The fabrication procedure of the MHN is as follows: design of the schematic circuit of the MHN; design of the PCB layout of the MHN \(see "Figure 1":http://www.nature.com/protocolexchange/system/uploads/3655/original/Figure_1.jpg?1432391113 ); assembly of the commercial chips, resistors and capacitors, onto the PCB; wire connection of the memristors with the PCB; and programming of the FPGA to control the MHN. 





**TIP**: There are two possible circuit configurations for the synaptic connection, as shown in "Figure 2":http://www.nature.com/protocolexchange/system/uploads/3657/original/Figure_2.jpg?1432391117. In the first configuration \(Figure 2\(a)), the synaptic weight of the synapse corresponding to input _Ni_ \(_i_=1, 2, 3) is _wi_=± _R_ /\(_Mi_ + _R_), where _Mi_ is the resistance of the corresponding memristor. In this design, _R_ should be of a high resistance at the level of 106 ohms in order to limit the current and avoid wrongly-switching of the memristor during circuit operation. _Mi_ can only be adjusted in the range from several tens of ohms to several hundreds of kΩ due to the memristor inherent property. As _R_ is much larger than _Mi_, _wi_ would be insensitive to _Mi_ and may always stay at ±1. Thus the variable range of the synaptic weight is very small. It is difficult for the MHN to detect such a small change in _wi_. In contrast, in the second configuration \(Figure 2\(b)), _wi_=± _Mi_/\(_Mi_ + _R_), thus the synaptic weight _wi_ is much more sensitive to the change of _Mi_ and can be varied in a larger range. Therefore, the circuit configuration shown in Figure 2\(b) is used to implement the synapses. 





**Implementation of associative memory in the MHN**


With a given pattern, the synaptic weight matrix elements in equation \(1) \(all equations in this protocol are placed in the "Supplementary document 1":http://www.nature.com/protocolexchange/system/uploads/3659/original/Supplementary_equation_file.pdf?1432386669) are set to _w_11= _w_22= _w_33=0, _w_12= _w_21, _w_13= _w_31, and _w_23= _w_32. The threshold vector **T**=\(_θ_1 _θ_2 _θ_3) is set as _θ_1= _θ_2= _θ_3= _θ_. Here, _wij_ \(_i_, _j_=1, 2, 3) is in the form of equation \(2). During the recalling process, the MHN is updated according to equation \(3). In equation \(3), _t_ denotes the number of updating cycles; _t_=0 denotes no updating taking place and the corresponding state vector is the initial vector **X**\(0); and the sign function is defined in equation \(4). In one updating cycle, new states of the neurons are asynchronously updated from _x_1, _x_2 to _x_3 in three stages, which are defined as stages a, b and c, respectively. 





**Single associative memory**


It is required that if the input is the target pattern itself, the final output must also stabilize at the target pattern. Thus, when “110” is stored into the MHN, according to equation \(3) and Hopfield network rule for updating, equation \(5) should be satisfied. With _w_11= _w_22= _w_33=0, _w_12= _w_21, _w_13= _w_31, and _w_23= _w_32 and _θ_1= _θ_2= _θ_3= _θ_, equation \(5) is simplified as shown in equation \(6). Equation \(6) can be satisfied with the following setting: _θ_=-2/60, _w_12=4/60, _w_13=1/60, and _w_23=-4/60. Thus the synaptic weight matrix is given by equation \(7), and the threshold vector is given by equation \(8). The following initial states **X**\(0) along with equations \(7) and \(8) are put into equation \(3) to verify the convergence: “000”, “001”, “010”, “011”, “100”, “101”, “110”, and “111”. It is found that the MHN can eventually converge to the final state “110” from the above initial states. 





Here, **X**\(0)= \(_x_\(0)1 _x_\(0)2 _x_\(0)3)=\(0 0 0) is taken as an example to demonstrate the recalling process. In stage a of the first updating cycle, we obtain equation \(9) according to equation \(3). And only _x_1 is updated in stage a of the first updating cycle, and thus we eventually obtain equation \(10) in this stage; In stage b of the first updating cycle, equation \(11) can be obtained according to equation \(3). And only _x_2 is updated in stage b, so we eventually obtain equation \(12) in this stage; In stage c of the first updating cycle, equation \(13) can be obtained according to equation \(3). And only _x_3 is updated in stage c, and thus we eventually obtain equation \(14). From equations \(9)-\(14), we can see that “000” eventually converges to “110”. In a similar way, the MHN converges to “110” from any other initial states. 





With the synaptic weight matrix shown in equation \(7), the resistance matrix of the memristors determined from equation \(2) can be set to the form of equation \(15). Note that it is not necessary to adjust the resistances of the memristors exactly to the above values because the MHN has a tolerance to the resistance variation. An offline training scheme for setting the resistance of the memristors to a pre-determined value is implemented with a C Language program embedded in the Keithley 4200 semiconductor characterization system. With the actual resistance matrix **M** in equation \(16), the actual synaptic weight matrix **W** was set to equation \(17). With the above synaptic weight matrixe **W** and the threshold vector in equation \(8), “110” can be correctly retrieved using the MHN fabricated on the PCB.





**Multi-associative memory**


Similar to the requirement for single associative memory, when the two patterns “000” and “101”, are stored in the MHN, equations \(18) and \(19) should be satisfied. With _w_11= _w_22= _w_33= 0, _w_12= _w_21, _w_13= _w_31, and _w_23= _w_32 and _θ_1= _θ_2= _θ_3= _θ_, equations \(18) and \(19) are respectively simplified as equations \(20) and \(21). Equations \(20) and \(21) can be satisfied with the following setting: _θ_=6/60, _w_12=1/60, _w_13=8/60, and _w_23=4/60. Thus the synaptic weight matrix is given by equation \(22), and the threshold vector is given by equation \(23). Putting equations \(22) and \(23) and **X**\(0) \(**X**\(0) can be varied from “000” to “111”) into equation \(3), “000” and “101” can be stored into and retrieved from the MHN theoretically. For the synaptic weight matrix given in equation \(22), the resistance matrix obtained from equation \(2) can be set to the form of equation \(24). The actual resistance matrix and the actual synaptic weight matrix of the fabricated MHN are given by equations \(25) and \(26), respectively:

The time cost to retrieve the pre-stored pattern in the 3-bit MHN depends on the initial state and the operational frequency. At 5 kHz operating frequency, the time required to retrieve the pre-stored pattern ranges from 33.3 μs to 300 μs depending on the initial states.

Failure to set the resistance matrix to the pre-determined one with appropriate precision may lead to the failure of associative memory. In this work, we set the memristors to a low resistance state first with a compliance current \(_e.g._, 0.1 mA, 1 mA, _etc._), and then the memristors are programmed with an offline training scheme which is implemented with a C Language program embedded in the Keithley 4200 semiconductor characterization system. In this way, the resistance matrix with appropriate precision can be obtained.

In the associated article, we demonstrated single associative memory and multi-associative memories in a 3-bit MHN. In the 3-bit MHN, the pre-stored pattern\(s) can be successfully retrieved at an operating frequency of 5 kHz. On the other hand, the simulation for a more complicated MHN consisting of 6561 synapses shows that more complicated patterns can be stored and retrieved but convergence errors may occur, as described in the associated article.

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This work was supported by NSFC under project No. 61274086 and the Young Scholar Fund of Sichuan under project No. 2011JQ0002, MOE Tier 1 Grant \(Grant No. RG 43/12) and NTU-A*STAR Silicon Technologies Centre of Excellence \(Grant No.M4070176.040).

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This protocol presents an approach to realize associative memory in a memristive Hopfield network \(MHN). In the MHN, neurons and synapse are constructed with operational amplifiers and memristors, respectively; and control signals are provided by field programming gate array \(FPGA). Different patterns can be stored into the MHN by appropriately setting the synaptic weight matrix and threshold matrix. In the process to recall the pre-stored pattern, the states of the neurons in the MHN are asynchronously updated in sequence under the control of FPGA.

Method Article

Y. Liu, T. P. Chen, S. G. Hu, Z. Liu, J. J. Wang, Q. Yu, L. J. Deng, Y. Yin, Sumio Hosaka

Y. Liu

Memristor group

Corresponding Author

T. P. Chen

Memristor group

Corresponding Author

S. G. Hu

Memristor group

Z. Liu

J. J. Wang

Q. Yu

L. J. Deng

Y. Yin

Sumio Hosaka

DOI:

10.1038/protex.2015.070

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Abstract

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Associative memory, Hopfield network, memristor

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Associative memory realized by a reconfigurable memristive Hopfield neural network

by S.G. Hu, Y. Liu, Z Liu, +6

Nature Communications (31 May, 2015)

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Y. Liu, T. P. Chen, S. G. Hu, Z. Liu, J. J. Wang, Q. Yu, L. J. Deng, Y. Yin, Sumio Hosaka

Y. Liu

Memristor group

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T. P. Chen

Memristor group

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S. G. Hu

Memristor group

Z. Liu

J. J. Wang

Q. Yu

L. J. Deng

Y. Yin

Sumio Hosaka

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